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a29040b series 512k x 8 bit cm os 5.0 volt-only, preliminary uniform sector flash m e mory document title 512k x 8 bit cmos 5.0 volt-onl y , uniform sector flash memor y revision histor y rev . no. histo r y issue date rem a r k 0.0 initial issu e janu ar y 14, 20 04 prelimi nar y 0.1 add pb-f ree p a ckag e t y p e jul y 6, 200 4 0.2 add the pro d u ct sp ec of -u se rie s (-40 c ~8 5 c) decemb er 6, 2 004 preliminary (decemb e r, 20 04, versio n 0.2 ) amic technology , corp.
a29040b series 512k x 8 bit cm os 5.0 volt-only, preliminary uniform sector flash m e mory features 5.0v r 10% for read an d w r ite operati ons access times: - 55/70/90 (max . ) current: - 20 ma t y p i cal active rea d cur r ent - 30 ma t y p i cal program/ e rase current - 1 p a ty p i cal c m os standb y f l exibl e sector architectur e - 8 uniform sect ors of 64 kb y t e each - an y c o mbi nati on of sectors can be er ased - supp orts full chip er ase - sector protecti on: a hard w a r e m e thod of prote c ting sectors t o prev en t an y in adv erten t program or er ase o perati ons w i t h in th at sector exte nde d o p e r ating tem pera t ure ran ge: -4 0 q c~+8 5 q c for ?u series embed ded era s e algorit hms - embed ded era s e algorithm w i ll automatica l l y erase the entire ch ip or an y comb inat i on of desi g n a ted sector s and ver i f y the erase d sectors - embed ded pr o g ram al gorithm automatica l l y w r it es an d verifies b y tes a t specified a ddr esses t y pic a l 1 00,00 0 progr am/eras e c y cl es per se ctor 20- ye ar data re tention at 1 2 5 q c - reli abl e op erat ion for the life of the s y stem compati b le w i t h jedec-stan dards - pino ut and s o ft w a r e comp atible w i th si ngle- po w e r- suppl y f l ash m e mor y sta n d a r d - superi o r in adv ertent w r ite pro t ection data pollin g an d toggle bits - provides a softw a r e metho d of detecting completio n of program or era s e oper ations erase susp en d/erase res u me - suspe nds a s e ctor erase ope ration to r ead data from , or program data to, a non- eras in g sector, then resumes the er ase op eratio n packag e optio ns - 32-pi n p-dip, plcc, or t s op (f or w a r d t y p e ) gener a l des c ription t he a29040b is a 5.0 volt-o nl y f l ash mem o r y or gan ize d as 524,2 88 b y t e s of 8 bits each. t he 512 kb y t es of data ar e further divi ded into ei ght secto r s of 64 kb y t es each for fle x i b l e sector erase capa bilit y. t he 8 bits of data app ear on i/o 0 - i/o 7 w h il e the addresses a r e input on a0 to a18. t h e a290 40b is offered in 32- pin pl cc, t s op, and pdi p packa ges. t h is device is d e sign ed to b e programm ed in- s y stem w i th the stan dard s y stem 5.0v olt vcc s u p p l y . additi ona l 12.0 volt vpp is not require d for in-s y s tem w r ite o r erase o perati ons. ho w e ver , the a2904 0 b can also b e programm ed i n standard epr om programm e rs. t he a29040b has a sec o n d togg le b i t, i/o 2 , to indicat e w h e t he r th e add re ssed se cto r i s b e i n g se l e cte d fo r e r a s e , and also offers the abil i t y to progr am in the erase suspen d mode . t he standard a290 40b offer s access times of 55, 70 an d 90 ns, allo w i n g hi gh-sp eed micr oproc essors to operate w i t h o u t w a it states. t o elimin ate b u s contentio n the device ha s separ ate chi p ena ble ( ce ), w r it e ena bl e ( we ) an d outp u t ena ble ( oe ) controls. t he device requires on l y a singl e 5.0 volt po w e r suppl y for b o t h rea d and w r i t e fu n c tio n s . in te rn al ly g e n e r a t e d and regul ated volta ges are provid ed for the program and era s e oper ations. t he a29040b is entirel y soft w a re command set compatibl e w i t h the jedec singl e-p o w e r-su ppl y f l ash standar d. comman d s ar e w r itten t o the comm and register usin g standar d microproc essor w r i t e timings. register contents serve as inp u t to an interna l state-machi ne that controls th e erase a nd pro g r amming circ uit r y . w r ite c y cles also i n terna l l y latch ad dres ses and data nee ded for the progr amming an d era s e operati ons . read in g data out of the d e v i ce is simi lar t o read in g from other f l ash or eprom devic es. device pro g ra mming occ u rs b y w r itin g the prop er pro g ra m command seq uenc e. t h is ini t iates the em b edd ed pr ogra m algor ithm - an interna l alg o rith m that automaticall y times the program puls e w i dths a nd veri fies prop er pro g ram margi n . device eras ure occurs b y executi ng the prop er eras e command s e q uenc e. t h is initiates the em bed ded eras e algor ithm - an intern al algor ithm that automatical l y prepro g rams t he arr a y (if it is not alre ad y progr ammed ) before e x ec uti ng the erase oper ation. dur i ng eras e, the device autom aticall y times t he erase p u l s e w i dths a n d verifies pro per erase mar g in. t he host sy st em can detect w heth e r a program or eras e oper ation is co mplete b y re ad ing the i/o 7 ( data polli ng) a n d i/o 6 (toggle) status bits. after a program or erase c y cle h a s bee n comp lete d, the d e vice i s read y to rea d arra y data o r accept an other command. t he sector era s e archit ecture allo w s memor y sect ors to b e erase d an d reprogr ammed w i t hout affe cting the d a t a contents of oth e r sectors. t he a2904 0b is fu ll y erase d w h e n shipp ed from the factor y . t he hard w a r e sector protecti on feature d i s ables o per atio ns for both progr a m and erase in an y com b in ati on of th e secto r s of memor y . t h is can be achiev ed v i a pro g rammin g equi pme n t. t he erase suspen d feature e nabl es the us e r to put erase on hold f o r an y p e riod of time to read data fr om, or progr a m data to, an y o t her sector that is not selec t ed for erasur e. t r ue backgrou nd eras e can thus be ac hiev e d . po w e r co nsum ption is gr eatl y reduc ed w h en the devic e is place d in the st and b y m ode. preliminary (decemb e r, 20 04, versio n 0.2 ) 1 amic technology , corp.
a29040b series pin configur ations dip plcc a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 0 i/o 1 i/o 2 i/o 3 vs s i/o 4 i/o 5 i/o 6 i/o 7 ce a1 0 oe a9 a8 a1 3 we a1 7 a1 4 vc c a1 1 a 2 9040b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a7 a6 a5 a4 a3 a2 a1 a0 i/ o 0 21 22 23 24 25 26 27 28 29 12 13 11 8 9 5 7 6 ce i/o 7 a1 0 a29040bl oe a1 1 a9 a8 a1 3 a1 4 i/ o 1 i/ o 2 vs s i/ o 3 i/ o 4 i/ o 5 i/ o 6 4 3 2 1 32 31 30 a1 2 a1 5 a1 6 a1 8 vc c we a1 7 14 15 16 17 18 19 20 10 tsop (for w a rd t y pe) a29040b v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a9 a8 a13 a14 a17 we vc c a18 a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a3 a2 a1 a0 i/o 0 i/o 1 i/o 2 vs s i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce a10 oe a11 preliminary (decemb e r, 20 04, versio n 0.2 ) 2 amic technology , corp.
a29040b series block diagra m state control command register address latch x-decoder y-decoder chip enable output enable logic cell matrix y-gating vcc detector pgm voltage generator data latch input/output buffers erase voltage generator vcc vss we ce oe a0 -a 18 i/o 0 - i/o 7 timer stb stb pin descrip tions pin no. de s c ription a0 - a18 address inp u ts i/o 0 - i/o 7 d a t a inputs/ou t p u t s ce chip e nab le we w r ite enabl e oe output enabl e v s s g r o u n d v c c p o w e r s u p p l y preliminary (decemb e r, 20 04, versio n 0.2 ) 3 amic technology , corp.
a29040b series absolu te ma ximum ratin g s* ambient oper a t ing t e mperatu r e ?. . . . . -55 c to + 125 c storage t e mperature . . . . . . . . . . ?. . . . -6 5 c to + 125 c vcc to ground . . . . . . . . . . . . . . . . . ?. . . . . -2.0v to 7.0 v output voltage (note 1) . . . . . . . . . . . . ?.. . . -2.0v to 7.0v a9 & oe (note 2) . . . . . . . . . . . . . . . . . . ?. -2.0 v to 12.5v all other pins (note 1) . . . . . . . . . . . . . . . . . ?-2.0v to 7.0v output short circuit curre nt (note 3) . . . . . . . ?. . . 200ma not e s : 1. minimum dc v o ltag e on inp u t or i/o pins is -0.5v. durin g voltag e transiti ons, inputs may und ersh oot vss to -2.0v for perio ds of u p to 20 ns. ma ximum dc vo lta ge o n outp u t and i/o pins is vcc +0.5v. during voltage transitions , outputs ma y o v ersho o t to vcc + 2 .0v for perio ds u p t o 20ns. 2. minimum d c i nput vo ltage o n a9 pi ns is - 0 .5v. duri ng voltag e transiti ons, a9 a nd oe ma y overs hoot vss to - 2.0v for perio ds of up to 20ns. ma xim u m dc input voltag e on a9 and oe is + 12.5v w h ich m a y ov e r shoot to 13.5v for peri o ds up to 20 ns. 3. no more than one outp u t is s horted at a tim e . durati on o f the short circuit shoul d not be greater tha n on e secon d . *c omment s stresses abov e those liste d und er "abs olute ma xim u m ratings " ma y cause permane nt damage to this device . t hese are stress ratings onl y. f unctio n al op eratio n of this device at these or an y oth e r conditi ons a b o ve those in dicat ed in the o per ati ona l se ctions of these specificati on i s not implie d or intend e d . expos ure to the abs olute m a ximum rati ng conditi ons for e x ten d e d per iod s ma y affect dev i c e relia bil i t y . opera t ing ranges commercial (c) de v i ces ambient t e mperature (t a ) . . . . . . . . . ?? . . . . 0 c to +70 c ex te nde d ra nge de v i c e s ambient t e mperature (t a ) . . . . . . . . . ?? .. -40 c to +85 c vcc supply volta g e s vcc for 10% devices ?.. ?.. . . . . . . . . . . +4.5v to +5.5 v operatin g ran ges defin e t hose limits betw e en w h ich th e function all y of the dev ice is gu arante ed. dev i ce bus opera t ions t h is section describ es the requirem ents and use of the device b u s operati ons, w h i c h are initiat ed throug h the intern al comm and r egister. t he comm and r egister itself do e s not occup y a n y address abl e memor y locati o n . t he register is compos ed of l a tches that st ore the comm ands, al ong w i th the ad dress a nd d a ta i n for m ation nee de d to e x ecute the command. t h e contents of th e regi st er serv e as in puts to t h e intern al state machin e. t he st ate machine outputs dictate the function of the devic e. t he appropri a te device b u s oper ations tabl e lists the input s and control levels req u ire d , and the resulti ng output. t he follo w i n g subs ections descr ib e each of thes e oper ations i n further deta il. t a b l e 1. a 2 9 0 40b de v i ce b u s op eratio n s op eratio n ce oe we a 0 ? a 18 i/o 0 - i/o 7 read l l h a in d out write l h l a in d in cmos standb y vcc 0.5 v x x x high-z t t l standb y h x x x high-z output disab le l h h x high-z leg end: l = logic lo w = v il , h = logic high = v ih , v id = 1 2 .0 0 . 5v , x = don ' t ca re, d in = data in, d out = da ta out , a in = add r ess in note: see the " s ector protecti on/un prot ection" section, fo r more information. preliminary (decemb e r, 20 04, versio n 0.2 ) 4 amic technology , corp.
a29040b series requir e ments for readin g array data t o read arra y data from the out puts, the s y stem must drive the ce and oe pins to v il . ce i s th e p o w e r con t ro l and selects the dev ice. oe is the output cont rol an d gates arra y data to the out put pins. we shoul d remai n at v ih all the tim e durin g re ad o p e ratio n . t he internal state m a chin e is set f o r readi ng arr a y data up on device po w e r- up, or after a hard w a r e rese t. t h is ensures that no spuri ous alterati on of the memor y c ontent occurs dur in g the po w e r transitio n. no command is n e cessar y i n th is mode to ob tain arra y dat a. standar d micr oproc essor re ad c y cles t h at assert vali d addr esses on the devic e addr ess inputs pro duce val i d dat a on the devic e data outp u ts. t he device remains en abl ed for read acc e ss un til the comman d regi ster co ntents are alter e d. see "r ea din g arra y data" for mo re information. refer to the ac read oper ations tabl e for ti ming specific ations an d to th e read operati o ns t i mings di a g ram for th e ti ming w a vefor m s, l cc1 in the dc characterist ics table repr esents the active current spec ific ation for rea d in g arra y data. writing commands/com mand seque nces t o w r ite a c o mmand or comm and s equ enc e ( w h i ch incl ud e s programm i ng data to the d e vice a nd er a s ing sectors of memor y ), the s y stem must drive we and ce to v il , a nd oe to v ih . an e r ase o perati o n can er ase o ne sector , multipl e sector s, or the entir e devic e. t he sector addre s s t ables indic a te the address ra nge that e a ch sector occup i e s . a "sector address" consists of the address inputs requ ired to uniq u e l y sel e c t a sector. se e the " c omm and defin i tion s" section for det ails on er asin g a sector or th e entire chi p , or suspe ndi ng/res u ming th e eras e oper ation. after the s y ste m w r ites th e a u tosel e ct command se qu enc e, the dev ice e n t e rs the a u tosel e ct mode. t he s y stem ca n the n read autos elec t codes from the in ter nal re gister ( w h i ch i s separ ate from the memor y arra y) on i/o 7 - i/o 0 . standar d read c y cl e ti mings a ppl y in this mo de. refer to th e "autosel ect mode" an d "aut oselect comm and seq uenc e " sections for mo re information. i cc2 in the c h a r acteristics tabl e repres ents th e active c u rren t specificati on f o r the w r ite m ode. t he "ac charact e ristic s" section conta i ns timing spec ificatio n tab l es and timin g diagr ams for w r ite oper ations. program an d erase ope r ation sta t us durin g an er a s e or progr a m operati on, the s y stem ma y check the stat us of the oper ation b y re adi n g the status bi ts on i/o 7 - i / o 0 . standard re a d c y cl e timing s and i cc read specificati ons appl y. r e fer t o "w rite oper ation status " for more inform ati on, an d to eac h ac ch aracte ristics section f o r timing di agr ams. sta ndby mode w hen the s y st em is not rea d i ng or w r itin g to the dev ice, i t can plac e the device in the standb y mo d e . in this mode, current co nsu m ption is gre a tl y r e d u ced, an d the o u tputs ar e place d in the h i gh imp eda nc e state, indep e n dent of the oe input. t he device en ters the cm os standb y mo de w h en the ce pin is h e ld at v cc 0.5v. (n ote that this is a more restrict ed voltag e range t han v ih .) t he device e n ters the t t l standb y mode w h en ce is held at v ih . t he devic e requir e s th e standar d acces s time (t ce ) before it is read y t o read d a ta. if the device is deselect ed d u ring er asure or programm i n g , the devic e dr a w s active c u rr ent unti l the op eratio n is complet ed. i cc3 in the dc charact e ristics t ables represe n ts the standb y current spec ific ation. outpu t dis a ble mode w hen the oe input is at v ih , output from the device i s disab l e d . t he output pins are placed in the high imp e d anc e state. table 2. sector addr ess e s table se c t or a 1 8 a 1 7 a 1 6 a d dr es s r a ng e s a 0 0 0 0 0 0 0 0 0 h - 0 f f f f h sa1 0 0 1 10000h - 1ffffh sa2 0 1 0 20000h - 2ffffh sa3 0 1 1 30000h - 3ffffh sa4 1 0 0 40000h - 4ffffh sa5 1 0 1 50000h - 5ffffh sa6 1 1 0 60000h - 6ffffh sa7 1 1 1 70000h - 7ffffh note: all sector s are 64 kby t es in size. preliminary (decemb e r, 20 04, versio n 0.2 ) 5 amic technology , corp.
a29040b series autosele c t mode t he autoselec t mode provi des man u facturer an d devi c e identific ation, and sector pr otection verification, through identifi e r co des output on i/o 7 - i/o 0 . t h is mode is prim aril y inten ded f o r pr ogrammi ng eq uipme n t to a u tomatical l y mat c h a devic e to be progr am med w i th its correspo ndi n g programm i ng algor ithm. ho w e ver, the auto s elect cod e s ca n also b e access ed in-s ystem th roug h the com m and re gister. w hen usi ng p r ogrammi ng e quipm ent, the autose l ect mo de requir e s v id (11.5v to 12.5 v) on address pina9. addre ss pins a 6 , a1, a nd ao must b e as sh o w n in a u tosel e ct co de s (high volta g e method) tabl e. in addition, w h e n verif y i n g sector protecti on, the s e ct or addr ess must app ear on th e appr opri a te hi ghest or der addr ess bits. refer to t h e correspo n d i ng sector address t ables. t he comman d definiti ons tabl e sho w s the remain in g addr ess bits that ar e don' t care. w hen all nec es sar y bits h a v e be en s e t a s requir ed, the programm i ng equi pme n t may the n read t h e correspo n d i ng identifi e r cod e on i/o 7 - i/o 0 .t o access the autose l ect cod e s in-s ystem, the host s y st e m can issue the autose l ect com m and vi a the c o mmand r e g i ster, as sho w n i n the comma nd definiti ons t able. t h is method does n o t requir e v id . see "comman d definiti ons" for details on usi n g the autose l ect mode. table 3. a29 040 b au tos e l ect co des (high voltage method ) d e s c r i p t i o n a 1 8 - a 1 6 a 15 - a 1 0 a9 a8 - a7 a6 a5 - a2 a1 ao identifier code on i/o 7 - i/o 0 manufactur e r id: amic x x v id x v il x v il v il 37h device id: a29 040b x x v id x v il x v il v ih 86h 01h (pr o tected) sector protecti on verification sector address x v id x v il x v ih v il 00h (u nprotect ed) contin uati on id x x v id x v il x v ih v ih 7 f h sector pro t e c tion/un protection t he hard w ar e sector prote c tion featur e disa bles bot h program an d e r ase op erati o n s in an y s e ctor . t he hard w a r e sector unprote c tion feature re -en abl es both program an d erase o perati o ns in prev i ous l y prot ected sec t ors. sector protecti on/un protectio n must be impleme n ted usi n g programm i ng equi pme n t. t h e proced ure requir e s a hig h voltag e (v id ) on addr ess pin a9 and th e con t rol pins. t he device is shipp ed w i t h all sectors unpr otected. it is possibl e to determin e w het her a secto r is protected or unpr otected. s ee "autos elect mode" for d e tai l s. hard w a r e da ta prot ection t he requirem ent of comm and unl ockin g sequ ence fo r programm i ng or erasin g pro v i des data pr otection ag ai n s t inadv ertent w r i t es (refer to the comma nd d e finitio n s tab l e ) . in add ition, the follo w i ng har d w a r e d a ta pr otection me asur es preve n t accid ental eras ure or programmi ng, w h ich mig h t other w i s e be cause d b y sp uri ous s y stem lev e l sign als duri n g v cc po w e r- up transitio ns, or from s y stem no i s e. t he device is po w e re d up t o rea d arra y da ta to avoi d acci denta l l y w r iti n g data to the arra y. write pulse "glitch" protection noise p u lses o f less than 5ns (typica l ) on oe , ce or we do not in itiate a w r ite c y cl e. logical inhibit w r ite cy c l es a r e inhi bited b y holdi ng an y one of oe =v il , ce = v ih or we = v ih . t o initiate a w r ite c y c l e, ce a nd we must be a logi cal zero w h ile oe is a logic a l o n e . po w e r-up write inhibit if we = ce = v il and oe = v ih durin g po w e r up, th e device d oes n o t accept commands on the rising edg e of we . t he internal state machine is automatical l y reset t o readi ng arr a y d a ta on the i n itia l po w e r- up. command definitions w r iting spec ifi c address an d data comma n d s or seq u e n c e s into the comm and re gister i n itiates dev ice oper ations. t he comman d de finitions tabl e defin es the valid r egist er command s e q uenc es. w r iting incorr ect ad dress an d dat a values or w r iti ng them in th e improp er se q uenc e resets t h e device to re adi ng arra y d a ta. all a ddress e s are l a tched on the fall ing ed ge of we or ce , w h ich e ver h a p pens l a ter. all data is latch ed on the ris i ng edg e of we or ce , w h ichever happens first. refer to the appr opri a te timing di agram s in the "ac characteristic s" section. rea d ing arr a y data t h e devi c e is au to ma ti ca lly se t to re ad ing a r ray data aft e r d e vi c e po w e r- u p . no co mm an ds ar e r e qu ir e d to retr i e v e dat a. t he d e v i c e i s a l s o r e ad y to r e ad a r r a y d a t a a f te r co mp le ti ng an embedd ed pro g ram or embedd ed era s e al go ri thm. afte r the d e vice a c cepts an er as e s u sp e nd co mm an d, t h e de v i c e e n t e r s th e era s e su sp e nd mo d e . t he s y st em c an re a d ar r a y dat a us in g th e st an d a r d re ad t i m i n g s , e xce pt t hat if i t rea d s a t a n a d d r ess w i thin e r a s e - su spe nded se cto r s, the d e vi c e out p u ts st at us d a t a . a f t e r c o m p l e t i n g a programm i ng oper ation in the erase sus pen d mode, the preliminary (decemb e r, 20 04, versio n 0.2 ) 6 amic technology , corp.
a29040b series s y stem ma y o n ce aga in rea d arra y d a ta w i t h the same exc epti on. se e "erase s u spe nd/erase resu me comma nds " for more inform ation o n this mode. t he sy stem must issue the reset command to re-enabl e th e device f o r rea d i ng arra y d a ta i f i/o 5 goes hi g h , or w h i l e i n th e autose l ect mod e . see the "re s et comman d " section, ne xt. see also "r e quirem ents for readi ng arra y data " in the "devic e bus o perati ons" s e ction for m o re i n formatio n . t h e read o perati o ns tabl e prov i des the r ead paramet ers, a nd read op eratio n t i mings diag ram sho w s the timing di agr am. res e t com m a nd w r iting the r e set comman d to the dev ice res e ts the dev ice t o readi ng arr a y data. addres s bits are do n' t care for this command. t he reset comman d ma y be w r itt en bet w e e n the sequ ence c y c l es in a n eras e comman d s equ ence befor e erasin g be gins. t h is resets the devic e to rea d ing arra y d a ta . once erasur e begi ns, ho w e ver, the devic e ign o res res e t commands unti l the oper ation is complet e . t he reset command ma y be w r itte n bet w e e n the se que nc e c y cl es in a program command se q uenc e before programm i ng b egins. t h is resets the device to readi ng arra y data (also a ppl ies to program ming in erase suspe nd mod e ) . once program ming be gins, ho w e v e r, the device i gnor es reset comman d s until the o p e r ation is com p l e te. t he reset command ma y be w r itte n bet w e e n the se que nc e c y cl es in a n a u tosel e ct command se que nc e. once in th e autose l ect mo de, the res e t command mu st be w r itten t o return to read ing arra y d a ta (also ap pli e s to autosele c t durin g erase s u spe nd). if i / o 5 goes hig h durin g a prog ram or erase o perati on, w r itin g the reset command returns the devic e to readin g arra y dat a (also a ppl ies d u ring er ase su spen d). autosele c t command sequenc e t he autoselect command s e q uenc e all o w s t he host s y ste m to access the manufactur e r and devic es codes, and determin e w h ether or not a sector is protected. t he comman d def i nitio n s tabl e sho w s the a d d ress an d dat a requir e ments. t h is method is an altern ative to that sho w n i n the autosel e ct codes (h ig h voltag e metho d ) table, w h ic h is inten ded for prom progra mmers and r equir e s v id on addr ess bit a9. t he autoselect command seq uenc e is initiat ed b y w r iti ng two unlock c y cles, follo w e d b y t he a u tosel e ct command. t he device th en e n ters the aut o s elect mod e , and th e s y st e m ma y re ad at an y addr ess an y numb e r o f times, w i th o u t initiati ng a noth e r comman d sequ ence. a read c y cle a t address xx0 0h retrieves the manufacture r code an d an other read c y cl e at xx03 h retrieves the contin uatio n code. a read cycl e at addres s xx01 h returns the device co d e . a read c y cl e contain i n g a sector addres s (sa) and the addr ess 02h i n return s 01 h if that sector is protected, or 00h if it is unprotected. re f e r to the sector address tab l es for valid sector address e s. t he sy stem must w r ite th e reset com m and to e x it the autose l ect mod e and retur n to readi ng arr a y d a ta. b y te program command sequence programmi ng i s a four-b us-c yc l e o perati on. t he program command se q uenc e is initiat ed b y w r iti ng tw o u n lock w r it e c y cl es, follo w ed b y the pr ogram set-up command. t h e program addr e ss and dat a a r e w r itten ne xt , w h ic h in turn initiate th e embed ded pro g ra m algorithm. t he s y stem is n o t requir ed to pr ovide furth e r controls or timi ngs. t he device automatic all y provid es i n tern all y g e n e rated progr am pu ls es and verif y the programme d cell margi n . t he comma nd definiti ons tabl e sho w s the a ddress an d da ta requirem ent s for the b y te pr o g ram comman d sequ ence. w hen the embed ded progr am algorithm i s complete, the device th en ret u rns to rea d in g arra y data a n d addr esses ar e no lo nger l a tched. t he s y stem can deter mine the statu s of the pro g ram o perati on b y u s ing i/o 7 or i/o 6 . see "write operatio n status" for informat i on o n these st atus bits. an y c o mma nd s w r itten to th e dev ice d u rin g the emb e d d e d program al gori t hm are ign o re d. programmi n g is all o w e d in an y se que nce and across s e c t or bou nd aries. a bit ca nnot b e programm ed from a "0" back to a "1 ". atte mpting to do so ma y halt th e oper ation an d set i/o 5 to "1", or caus e th e data pollin g alg o ri thm to indica te the operat ion w a s successful. h o w e ver, a s u cc eedi ng r e a d w i ll sh o w th at the data is still "0". onl y erase op er atio ns can convert a "0" to a "1". start write program command sequence data poll from system verify data ? last address ? programming completed no yes yes increment address embedded program algorithm in progress note : see the appropriate command definitions table for program command sequence. figure 1. program operation preliminary (decemb e r, 20 04, versio n 0.2 ) 7 amic technology , corp.
a29040b series chip erase command s e quen ce chip eras e is a six-bus-c yc le oper ation. t he chip erase command se q uenc e is initiat ed b y w r itin g tw o unl ock c y c l es, follo w e d b y a set-up comma nd. t w o ad diti onal un lock w r i t e c y cl es are the n follo w e d b y the chip er ase command, w h i c h in turn i n vok e s the embe dd e d erase alg o rit h m. t he devic e does not requi re the s y stem to prepr ogram prior to eras e . t he embedde d erase alg o rithm automatica l l y pr epro g ram s and ver i fies th e entire mem o r y for an a ll z e ro data p a tter n prior to el ectri c al eras e. t h e s y stem is not requ ire d to provid e an y co ntrols or timi ng s during thes e oper ations. t h e comman d def i nitio n s tabl e sho w s the a d d ress an d dat a requir e ments f o r the chip er a s e comman d sequ ence. an y c o mman d s w r itte n to the chip duri ng the embe dde d erase al gorith m are ign o red. t he s y stem c an determ i ne t h e status of the erase o perati on b y usi ng i/o 7 , i / o 6 , or i/ o 2 . see "w rite operati on status" for i n formatio n on these status bit s . w hen the embed ded era s e algor ithm is complete, th e device ret u rns to readin g arr a y d a ta an d a ddress e s are no long er latch ed. figure 2 illustr a tes the algorit hm for the erase operati on. see the erase/prog ram operation s t ables in "ac characteristic s" for parameter s, and to the ch ip/sector erase operati o n t i mings for timing w a v e forms. sector era s e command sequen ce sector eras e i s a si x-bus-c ycle op erati on. t he sector era s e command se q uenc e is initiat ed b y w r itin g tw o unl ock c y c l es, follo w e d b y a set-up comma nd. t w o ad diti onal un lock w r i t e c y cl es are then follo w e d b y the addr ess of the sector to be erase d , and the sector era s e command. t he command definiti ons tabl e sho w s the a ddress an d da ta requirem ent s for the sector erase comman d seque nce. t he device do es not requ ire t he s y stem to prepro g ram th e memor y pri o r to erase. t he embed de d erase al gorith m automatic all y p r ograms a nd v e rifies th e sect or for an all z e r o data pattern p r ior to electric al erase. t he s y stem is no t requir ed to provide an y co n t ro ls or timings during thes e oper ations. after the com m and se qu enc e is w r itten, a s e ctor eras e time- out of 50 s b egins. duri ng the time-out period, ad ditio n a l sector ad dres ses an d sect or eras e com m ands m a y b e w r itte n. load in g the sector erase buffer ma y be done i n an y sequ ence, a n d the num ber of sectors ma y be from o ne sector to all sectors. t he time bet w e e n these add ition a l c y cles must be less than 50 s, other w i se t he l a st ad dres s and c o mman d might n o t be accepte d , an d eras ure ma y begi n. it is recommen d e d that processor interrupts be disab l e d dur in g this time t o ens ure a ll commands ar e accepte d . t he interrupts ca n be re-e na bl ed after the l a st sector erase command is w r itten. if the time bet w een additi on al sect or erase com m ands can b e assumed to be less than 50 s, the sy stem need not monitor i/o 3 . an y command ot he r than sector eras e or erase suspe nd dur in g the time-o ut p e riod r e sets th e devic e to re adin g arr a y da ta. t he sy stem must re w r ite the command seque nce and a n y additi on al sect or addr esses a nd comma nds. t he sy st em ca n monit o r i/o 3 to determi ne if the sector eras e timer has time d out. (see t h e " i/o 3 : sector erase t i mer" section.) t he ti me-out b egi ns from the risi ng edg e of th e fin a l we pulse i n the co mmand se que nce. once the sector erase opera t ion has beg un , onl y the erase suspe nd com m and is val i d . all other commands ar e ignor ed. w hen the embed ded era s e algor ithm is complete, th e device ret u rns to readin g arr a y d a ta an d a ddress e s are no long er l a tched. t he s y stem c an d e termin e the status of th e erase op eratio n b y usin g i/o 7 , i/o 6 , or i/o 2 . refer to "writ e operatio n status" for informat i on o n these st atus bits. f i gure 2 ill ustrates the al gori t hm for the er ase op erati on. refer to the erase/progr am o perations tables in the "ac charact e ristics " section for par ameters, an d to the sector erase operati o ns t i ming diag ram for timing w a veforms. erase susp e nd/erase re sume comm ands t he erase suspen d comman d allo w s the s ystem to interrupt a sector erase operati on a nd then read data from, or program d a ta to, an y sector not selected for erasure. t h is command is v a lid o n l y d u rin g the sector e r ase op eratio n , inclu d in g the 5 0 s time-out p e riod duri ng th e sector er ase command se q uenc e. t he erase suspe n d command i s ignor ed if w r i tten durin g t he chip er as e oper ation or embed ded pr ogram al gorith m . w r iting the erase suspe n d command dur i ng the sector erase time- o ut immed i atel y terminates the time-out peri od an d suspe nds the eras e oper ation. ad dresses are " don' t cares" w h en w r iti ng the erase susp en d comman d . w hen the erase suspen d command is w r itten durin g a sector erase o perati on, the device req u ires a maximum o f 20 s to susp e nd the eras e oper ation. h o w e ver, w h en t he erase susp en d comman d is w r itte n dur ing t he sector er as e time-out, the device immed i atel y termin a t e s the time- o ut perio d an d sus pen ds the eras e oper ation. after the erase oper ation has bee n susp en d ed, the s y stem can read arra y data from or pr ogram dat a to an y sector n o t selecte d for erasure. (t he device " e ras e suspe nds" al l sectors selecte d for erasure.) normal re ad a nd w r ite timin g s and comma nd definitio ns ap pl y . re adi ng at an y ad dres s w i t h in erase-s u spe nde d sec t ors produc es status data on i/o 7 - i/o 0 . t he s y stem ca n use i/o 7 , or i/o 6 and i/o 2 together, to d e termine if a sector is activ e l y erasi ng or is erase-sus p e n d ed. see "w ri te operatio n status" for informatio n on these status bit s . after an erase - suspe nde d pr ogram o perati on is com p let e , the s y stem ca n once ag ain read arra y d a ta w i t h in n o n - suspended sec t ors. t he sy st em can determi ne the status o f the progr am o perati on usi ng the i/o 7 or i/o 6 status bits, just as in the standard progr am operat i on. see "w rite operatio n status" for more information. t he sy stem ma y also w r i t e the autos elect comma n d sequ ence w h e n the devic e is in the erase suspe nd mod e . t he device allo w s re adi n g autos elect codes even at addr esses w i t h in eras ing se ctor s, since the codes are n o t stored in the memor y arr a y . w hen the device e x its the autose l ect mode, the device re verts to the erase suspend mode, and is read y for a not her val i d oper ation. se e "autosel ect co mmand se que nce" for more i n formatio n . t he s y stem must w r ite th e erase res u me comma n d (address bits are "d on' t car e ") to e x it the erase sus p e n d mode a nd co ntinu e the se ctor erase op eratio n. f u rther w r it es of the r e sume comm a nd are i g n o red . another eras e suspe nd com m and can b e w r itten after the device h a s resumed erasi ng. preliminary (decemb e r, 20 04, versio n 0.2 ) 8 amic technology , corp.
a29040b series preliminary (decemb e r, 20 04, versio n 0.2 ) 9 amic technology , corp. start write erase command sequence data poll from system data = ffh ? erasure completed yes embedded erase algorithm in progress note : 1. see the appropriate command definitions table for erase command sequences. 2. see "i/o 3 : sector erase timer" for more information. no figure 2. erase operation
a29040b series table 4. a29 040 b comm and de finitio n s bu s c y cle s (n o t es 2 - 4) firs t s e c o n d t h i r d f o u r t h f i f t h six t h command se que nc e (no t e 1) cycle s ad d r d a t a ad d r d a t a ad d r d a t a ad d r d a t a ad d r d a t a ad d r d a t a read (n ote 5) 1 ra rd reset (note 6) 1 xxx f 0 manufactur e r id 4 555 aa 2aa 5 5 555 90 x0 0 37 device id 4 555 aa 2aa 5 5 555 90 x0 1 86 contin uati on id 4 555 aa 2aa 5 5 555 90 x0 3 7 f 0 0 autoselect (note 7) sector protect verif y (note 8) 4 5 5 5 aa 2aa 5 5 555 90 sa x0 2 0 1 p r o g r a m 4 5 5 5 aa 2aa 5 5 555 a0 pa p d chip eras e 6 5 5 5 a a 2aa 5 5 555 80 555 a a 2 a a 5 5 555 10 sector erase 6 555 aa 2aa 5 5 555 80 555 aa 2aa 55 sa 30 erase susp en d (note 9) 1 xxx b0 erase res u me (note 10) 1 xxx 30 leg end: x = don' t care ra = address of the memor y locatio n to be r ead. rd = data rea d from locatio n ra durin g rea d oper ation. pa = address of the mem o r y l o cati on to be pr ogramm e d. address e s l a tch on the fa llin g e dge of t he we or ce puls e , w h ich e ver h a p pens l a ter. p d = data to b e programmed at lo cation pa. data la tches on the ri sing edge of we or ce pulse, w h ichever happens first. sa = address of the sector to be verifie d (in autose l ect mod e ) or erase d . address b i ts a18 - a16 select a uni que sect o r . note: 1. see t able 1 fo r descriptio n of bus oper ation s . 2. all valu es are i n he xa decim al. 3. exce pt w h e n readi ng arr a y or autosel ect dat a, all bus c y cl e s are w r ite op e r ation. 4. address b i ts a18 - a11 are d on' t cares for unlock a nd com m and c y cl es, unless sa or pa require d. 5. no unl ock or c o mmand c y cl e s require d w h e n read ing arr a y data. 6. t he reset co mmand is req u i red to r e turn t o rea d in g arra y data w h e n de vice is i n the a u tosel e ct mod e , or if i/o 5 goes hi g h ( w h i l e the dev i c e is provi d in g status data). 7. t he fourth cy c l e of the autose l ec t comman d sequ ence is a r ead c y cl e. 8. t he data is 00h for an unprot ected sect or a nd 01h for a pr otected sector. see "autosel e c t command sequ ence " for more information. 9. t he sy stem m a y re ad a nd pr ogram in non- e r asing s e ctors, or enter the a u toselect mo de, w h en i n the er ase susp en d mode. 10. t he erase re sume comman d is va lid onl y durin g the eras e suspe nd mo de. preliminary (decemb e r, 20 04, versio n 0.2 ) 10 amic technology , corp.
a29040b series write o p era t ion status start read i/o 7 -i/o 0 address = va i/o 7 = data ? fail no note : 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. i/o 7 should be rechecked even if i/o 5 = "1" because i/o 7 may change simultaneously with i/o 5 . no read i/o 7 - i/o 0 address = va i/o 5 = 1? i/o 7 = data ? yes no pass yes yes figure 3. data polling algorithm several bits, i/o 2 , i/ o 3 , i/o 5 , i/o 6 , and i/o 7, are provi ded i n the a29 0 4 0 b to determ i ne t h e st atus of a w r it e o perati o n . t able 5 and th e follo w i n g sub s ections d e scri be the fu nction s of these status bits. i/o 7 , i / o 6 and i/o 2 each offer a method for determini n g w h ether a pr ogram or er ase oper atio n is complet e or in progress. t hese three bits are discusse d first. i/o 7 : data poll ing t he data polling bit, i/ o 7 , indicates to the host sy stem w h eth e r an embed ded al gorithm is in progress or complet ed, or w h eth e r the de vice is in eras e suspen d. data polli ng is vali d after the rising edg e of the final we puls e i n the progr am or erase comma nd seq uenc e. durin g the embed ded progr a m algorithm, the device outp u t s on i/o 7 the co mpleme nt of the datum prog rammed to i/o 7 . t h is i/o 7 statu s also app lies to progr ammi ng d u rin g era s e suspe nd. w hen the emb edd ed progr a m algorithm is complet e , the device out puts the dat um pro g r ammed to i/o 7 . t he sy stem m u st provid e the program a ddr ess to read val i d status informati on on i/o 7 . if a program addr ess falls w i t h in a protected sec t or, data pollin g on i/o 7 is active for appr o x imate l y 2 s, then the device r e turns to readi ng arra y data. durin g the embed ded er ase al gorithm , data polli n g prod uces a "0" on i/o 7 . w hen the embe dd ed erase a l gor ith m is complete, or if the device en ters the erase suspe nd mode , data pollin g pro duc es a "1" o n i/o 7 .t his is analo gous to th e complem ent/true datum output described for the embedded program a l gor i t hm: the erase func tion c han ges al l the b i ts i n a sector to "1"; prior to this, the devi c e outputs th e "compl ement," or "0." t he s ystem must pro v ide an a ddr es s w i t h in an y of t he sectors s e l e cted for er as ure to rea d va lid status informati on on i/o 7 . after an erase command se que nce is w r itten, if all secto r s selecte d for erasing ar e prot ected, data polling on i/o 7 is active for appr oximatel y 1 0 0 s, then the device returns t o readi ng arra y data. if not all se lecte d sectors are protected , the embedd e d erase algo rith m erases the unprotect e d sectors, and ig nores the se lec t ed sectors tha t are protected. w hen the s ystem detects i/o 7 has ch ang ed from the complem ent to true data, it c an re ad va lid d a ta at i/o 7 - i/o 0 on the foll o w i ng rea d c y c l e s . t h is is because i/o 7 ma y chan ge as yn c h ron ousl y w i th i/o 0 - i/o 6 w h i l e output e n a b l e ( oe ) is asserted lo w . t he data polling t i mings (durin g embed ded al gorithms) fi gur e in th e "a c char acteristic s" section il lustrat e s this. t able 5 sho w s the o u tputs for data polling on i/o 7 . f i gure 3 sho w s the data pollin g al gorithm. preliminary (decemb e r, 20 04, versio n 0.2 ) 11 amic technology , corp.
a29040b series i/o 6 : toggle bit i t oggle bit i on i/o 6 indicates w h eth e r an em bed ded pr ogra m or erase al gori t hm is in pro g r e ss or compl e te, or w h eth e r th e device h a s ent ered the eras e suspe nd mo de. t oggle bit i ma y be rea d at an y ad dress, and is valid aft e r the rising ed ge of the fin a l we pulse i n the c o m m and s equ enc e (pri or t o the program or eras e operatio n), and during the sector eras e time-out. durin g an em b edd ed pro g ra m or erase a l g o rithm op erati o n, successive r e ad c y c l es to any address c a use i/o 6 to toggle. (t he sy stem ma y us e eith e r oe or ce to control the rea d c y cl es.) w hen the oper ation i s complete, i/o 6 stops togglin g . after an erase command se que nce is w r itten, if all secto r s selecte d for erasi ng ar e protected, i / o 6 toggles for appr o x imate l y 100 s, then returns to readin g arra y data. if not al l se lecte d sectors are protected, th e embed ded era s e algor ithm eras es the un prot ec ted sectors, and i gnor es th e selected sector s that are prote c ted. t he sy stem c an us e i/o 6 a nd i/o 2 together to determi n e w h eth e r a sector is activel y e r asing or is er ase-sus pen de d. w hen the devi c e is activ e l y er asin g (that is , the embed de d erase a l gor ith m is in pro g r e ss), i/o 6 toggles. w h e n t he device e n ters the erase susp end mod e , i/o 6 stops toggli n g. ho w e v e r, the s y stem must als o use i/o 2 to determine w h ich sectors are er asing or er as e- susp end ed. alternativ el y, the s y stem ca n us e i/o 7 (see the subsecti on on " i/o 7 : data polli ng"). if a program addr ess falls w i t h in a prote c ted sector, i/o 6 toggl es for a p p ro ximate l y 2 s after the pr ogram command sequ ence is w r itten, then retur n s to readi ng a rra y d a ta. i/o 6 also toggl es durin g the er ase-sus p e n d - program mo d e , and stops to gg ling once th e embed ded pro g r am alg o rithm i s complet e . t he w r ite operatio n status table sh o w s the outputs for t oggle bit i o n i/o 6 . refer to f i gure 4 for the toggle b i t algor ithm, and to the t oggle bit t i mings fi gure in the "a c charact e ristics " section for th e timing diagr a m . t he i/o 2 vs . i/o 6 figure show s the differe nces bet w e en i/o 2 and i/o 6 in grap hica l form. see als o the subsecti on o n " i/o 2 : t oggle bit ii". i/o 2 : toggle bit ii t he " t oggle b i t ii" on i/o 2 , w h en used w i t h i/o 6 , indicat e s w h eth e r a p a rticular s e ctor is activel y erasi ng (that is, th e embed ded era s e algor ithm is in progress), or w h ether tha t sector is eras e-susp end ed. t oggle bit ii i s valid after th e rising ed ge of the final we p u l se i n th e co mma nd sequ ence. i/o 2 toggles w h en th e s y stem reads at addr esses w i t h i n those sectors that have be en se lecte d for erasure. (t he s y stem ma y use either oe or ce to control th e read cy cles.) but i/ o 2 cannot distingu ish w h eth e r the sector is activel y eras in g or is erase-s u spe nde d. i/o 6 , by co mp a r i s on , indic a tes w h et her the d e vic e is activel y erasin g, or is in erase suspe n d , but cannot distingu ish w h ich sectors a r e selecte d for er asure. t hus, b o th status b i ts are re quir ed fo r sector and mo de inform ation. refer to t able 5 to compar e outputs for i/o 2 and i/o 6 . f i gure 4 sho w s the toggle bit algor ithm in flow c h art form, a n d the sectio n " i/o 2 : t oggle bit ii" exp l ai ns the algor ithm. se e also the " i/o 6 : t oggle bit i" subsecti on. refer to the t oggl e bit t i mings figure for the toggle bit timing d i agram. t he i/o 2 vs. i/o 6 figure sho w s the diffe rences bet w e e n i/o 2 and i/o 6 in grap hica l form. rea d ing tog gle bits i/o 6 , i/o 2 refer to f i gure 4 for the follo w i ng discuss io n. w henever t h e s y stem in itial l y begins re adi n g t oggl e bit status, it must rea d i/o 7 - i/o 0 at l east t w ic e in a ro w to d e ter m ine w h ether a toggl e bit is toggl in g. t y pic a ll y, a s y stem w o uld n o te a n d store the va lu e of the tog g le bit after the fir s t read. after the secon d read, the s y stem w o ul d comp are the ne w val ue of the toggl e bit w i th the first. if the togg le b i t is not toggl in g, th e device h a s complete d the progr am or eras e operati on. t h e s y stem can re ad arra y data on i/o 7 - i/o 0 on the follo w i n g read c y cl e. ho w e v e r, if after the initial t w o re ad c y cl es, the s y ste m determin e s tha t the toggl e bit is still tog g li ng, the s y stem als o shoul d n o te w h ether the val u e of i/o 5 is high (see the s e ctio n on i/o 5 ). if it i s , the sy stem should the n determin e aga i n w h eth e r the toggle b i t is togg lin g, since the toggle b i t ma y have stop ped t oggl in g just as i/o 5 w ent hi gh. if the toggle b i t is no l o n ger to ggli ng, the dev ice h a s succes s full y comp lete d the progr am or erase o per ation. if it is still toggl ing, th e device di d not complet e the operati on succe ssfull y , an d the s y stem must w r it e the reset command to return to readi n g arra y data. t he remainin g scenari o is that the s y stem in itiall y d e termin e s that the toggle bit is toggli ng a nd i/o 5 has not gone hi gh. t h e s y stem ma y c ontin ue to mo nitor the tog g l e bit an d i/o 5 throug h succe ssive rea d c y c l es, determi nin g the status a s describ ed in the previo us p a ragr a ph. alte rnativel y, it ma y choos e to per form other s y stem tasks. in this case, th e s y stem must s t art at the begi nni n g of the al gorithm w h en i t returns to determine the status of the operatio n (top of f i gure 4). i/o 5 : exceed ed timing limits i/o 5 indicates w h ether the program or erase time ha s exc e e ded a sp ecified inter nal puls e co unt li mit. under th e s e conditi ons i/o 5 prod uces a "1. " t h is is a fail u r e con d itio n th at indic a tes the program or er ase c y cle w a s not successfu l l y complet ed. t he i/o 5 failur e cond ition ma y a ppe ar if the s y stem tries to program a " 1 " t o a loc a tio n th at is prev io usl y progr ammed t o "0." onl y an er ase op eratio n can cha nge a "0" back to a "1 . " under this co nditio n , the dev ice ha lts the operati on, a n d w h en t he o p e r ation h a s e xceed ed the ti ming l i mits, i/o 5 prod uces a "1." under b o th the s e conditi ons, the s y stem mus t issue the rese t command to re turn the devic e to readin g arra y dat a. i/o 3 : sector erase timer after w r iti ng a sector erase c o mmand s e q u ence, the s y st em ma y r ead i/o 3 to determin e w heth e r or not an er as e oper ation has beg un. (t he sector erase time r does n o t app l y to the chip erase comma nd.) if additional sectors a r e selecte d for er asure, the e n ti re time-out als o app lies after each a dditi ona l sector erase co mmand. w h e n the time-out i s complet e , i/o 3 s w itc hes fro m "0" to " 1 ." t he sy st em ma y ignor e i/o 3 if th e s y stem can g uara n tee that the time bet w e e n additi on al sector erase com m ands w i l l al w a y s b e less than 50 s. see als o the "sector erase comm and se qu ence " section. preliminary (decemb e r, 20 04, versio n 0.2 ) 12 amic technology , corp.
a29040b series start read i/o 7 -i/o 0 toggle bit = toggle ? program/erase operation not commplete, write reset command yes notes : 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as i/o 5 changes to "1". see text. no read i/o 7 - i/o 0 twice i/o 5 = 1? toggle bit = toggle ? yes yes program/erase operation commplete no no read i/o 7 -i/o 0 (notes 1,2) figure 4. toggle bit algorithm (note 1) after the sector eras e com m and s equ en ce is w r itte n, the s y stem shou ld read the status on i/o 7 ( data polli ng) or i/o 6 (t oggle bit 1 ) to ensur e the d e vice ha s accepte d the command se q uenc e, and th en read i/o 3 . i f i/ o 3 is "1", the intern all y co ntrolle d eras e c y cl e has b e gun; al l furth e r commands ( o ther than er ase su spen d) are ignor ed u n til th e erase op eratio n is complete. if i/o 3 is "0", the device w i ll accept add itio nal sector er a s e commands. t o ensure the command h a s been accepte d , the sy stem soft w a re sho u ld check the status of i/o 3 prior to an d foll o w i ng e a ch subse que nt se ctor erase co mmand. if i/o 3 is high on t h e secon d status check, the la st command m i g h t not have be en accepte d . t able 5 sho w s the outputs for i/o 3 . preliminary (decemb e r, 20 04, versio n 0.2 ) 13 amic technology , corp.
a29040b series table 5. write opera t ion statu s i/o 7 i / o 6 i / o 5 i / o 3 i / o 2 op eratio n (no t e 1) (no t e 2) (no t e 1) embed ded pro g ram alg o rithm 7 i/o t o g g l e 0 n / a n o togg l e standar d mode embed ded era s e algorit hm 0 t oggle 0 1 t oggle read in g w i thi n erase suspe nde d se ctor 1 n o togg l e 0 n / a t o g g l e read in g w i thi n non-eras e suspend sector d a t a d a t a d a t a d a t a d a t a erase suspe nd mode erase-sus pen d-program 7 i/o t o g g l e 0 n / a n / a notes: 1. i/o 7 and i/o 2 re quire a vali d ad dress w h en re adin g status inf o rmation. r e fe r to the appro p r iate subs ectio n for further de tails. 2. i/o 5 s w itche s to ?1? w h en a n embed ded p r ogram or emb edd ed er ase o perati on has e x ce ed ed the m a ximum timin g limits. see ?i/o5: ex ceeded t i ming limits? for more information. maximum negativ e input ov ershoot 20ns 20ns 20ns +0.8v -0.5v -2.0v maximum positiv e input o v ershoot 20ns 20ns 20ns vcc+0.5v 2.0v vcc+2.0v preliminary (decemb e r, 20 04, versio n 0.2 ) 14 amic technology , corp.
a29040b series dc char ac te ristics ttl/nmos co mpa t ible para mete r sy mbol pa rame ter des c r iption te s t de sc ription min. ty p. ma x . unit i li input loa d cur r ent v in = vss to v cc. vcc = vcc max 1.0 a i lit a9 input lo ad current vcc = vcc max, a9 = 12.5v 100 a i lo output leak ag e current v out = vss to vcc. vcc = vcc max 1.0 a i cc1 vcc active re ad curre nt (notes 1, 2) ce = v il , oe = v ih 2 0 3 0 ma i cc2 vcc active w r ite (program/er a se) current (notes 2, 3, 4) ce = v il , oe =v ih 3 0 4 0 ma i cc3 vcc stand b y current (note 2) ce = v ih 0 . 4 1 . 0 ma v il input lo w l e ve l -0.5 0.8 v v ih input hig h lev el 2.0 vcc+ 0.5 v v id voltage for autoselect and sector pro t ect vcc = 5.25 v 10.5 12.5 v v ol output lo w vo ltage i ol = 12ma, vcc = vcc min 0.45 v v oh output high v o ltag e i oh = -2.5 ma , vcc = vcc min 2.4 v cmos compatible para mete r sy mbol pa rame ter des c r iption te s t de sc ription min. ty p. ma x . unit i li input loa d cur r ent v in = vss to v cc, vcc = vcc max 1.0 a i lit a9 input lo ad current vcc = vcc max, a9 = 12.5v 100 a i lo output leak ag e current v out = vss to vcc, vcc = vcc max 1.0 a i cc1 vcc active re ad curre nt (notes 1,2) ce = v il , oe = v ih 2 0 3 0 ma i cc2 vcc active program/eras e c u rrent (notes 2,3,4) ce = v il , oe = v ih 3 0 4 0 ma i cc3 vcc stand b y current (notes 2, 5) ce = vcc 0.5 v 1 5 a v il input lo w l e ve l -0.5 0.8 v v ih input hig h lev el 0.7 x vc c vcc+ 0.3 v v id voltag e for autoselect a nd se ctor protect vcc = 5.25 v 10.5 12.5 v v ol output lo w vo ltage i ol = 12.0 ma, vcc = vcc min 0.45 v v oh1 i oh = -2.5 ma, vcc = vcc min 0.85 x vcc v v oh2 output high v o ltag e i oh = -100 a. vcc = vcc min v c c - 0 . 4 v notes for dc characteristics ( both tabl es): 1. t he i cc current listed incl ud es both the dc o perati on curre n t and the frequ enc y de pen de nt compon ent (at 6 mhz). t he frequenc y compo nent t y pi call y is less th a n 2 ma/mhz, w i th oe at v ih . 2. maximum i cc specificati ons ar e tested w i th v cc = vcc max. 3. i cc active w h i l e embedd ed al gorithm (pro gr am or erase) is in progr ess. 4. not 100 % tested. 5. f o r cmos mode on l y , i cc3 = 2 0 a ma x a t ex te nd ed te mp era t u r e s (> +8 5 c) preliminary (decemb e r, 20 04, versio n 0.2 ) 15 amic technology , corp.
a29040b series ac char ac te ristics read only operations para mete r s y mbols sp eed jedec std de s c r i p t i o n t e s t se tup - 5 5 - 7 0 -90 unit t av a v t rc read c y c l e t i me (note 2) min. 55 70 90 ns t av q v t ac c address to output del a y ce = v il oe = v il max . 55 70 90 ns t elqv t ce chip e nab le to output dela y oe = v il max . 55 70 90 ns t glqv t oe output enabl e to output dela y max . 30 30 35 ns read min. 0 0 0 ns t oeh output enabl e hold t i me (note 2) t oggle and data pollin g min. 10 10 10 ns t eh qz t df chip enable to output high z (notes 1,2) max . 1 8 2 0 20 ns t ghqz t df output enabl e to output high z (notes 1,2) max. 18 20 20 ns t ax q x t oh output hold t i me from addresses, ce or oe , whichever occurs first min. 0 0 0 ns notes: 1. output driver d i sabl e time. 2. not 100 % tested. timing wav e forms for read only op eration addresses addresses stable ce oe we output valid high-z output t rc t oeh t oe t ce high-z t oh t df t acc 0v preliminary (decemb e r, 20 04, versio n 0.2 ) 16 amic technology , corp.
a29040b series ac char ac te ristics eras e an d pro g r am op erati o n s para mete r s y mbols sp eed jedec std de s c ription - 5 5 - 7 0 -90 unit t av a v t wc w r ite c y cl e t i me (note 1) min. 55 70 90 ns t av w l t as address setu p t i me min. 0 ns t wla x t ah address h o ld t i me min. 40 45 45 ns t dv w h t ds data setup t i me min. 25 30 45 ns t w hdx t dh data hol d t i me min. 0 ns t oes output enabl e setup t i me min. 0 ns t ghwl t ghwl read r e cov e r t i me before write ( oe high to we lo w ) min. 0 ns t elwl t cs ce setup t i me min. 0 ns t wh eh t ch ce hold t i me min. 0 ns t wl wh t wp w r ite pulse w i dth min. 30 35 45 ns min. 20 ns t wh wl t wph w r ite pulse w i dth hig h max . 50 s t wh wh 1 t wh wh 1 b y te pro g ram m ing oper atio n (note 2) ty p . 7 s t wh wh 2 t wh wh 2 sector erase operatio n (note 2) ty p . 1 sec t vc s vcc set up t i me (note 1) min. 50 s notes: 1. not 100 % tested. 2. see the "eras e and progr am ming perfo rma nce" secti on fo r more informat i on. preliminary (decemb e r, 20 04, versio n 0.2 ) 17 amic technology , corp.
a29040b series timing wav e forms for program ope r ation timing wav e forms for chip/sector e r ase op era t ion addr esse s ce oe we dat a vc c a0h p d t wc pa pr og ra m command se quen ce (l ast t w o cycl e s ) pa d ou t ~ ~ ~ ~ pa ~ ~ st at us ~ ~ ~ ~ ~ ~ ~ ~ t as t vc s read st a t us dat a ( l ast t w o c ycl es ) 555h t ah t wh w h 1 t ch t gh w l t wp t wph t cs t ds t dh not e : pa = p r o g r a m a ddr ss, pd = pr ogr am dat a, dout i s t he t r ue da t a at t h e p r o g ra m ad dr ess. ad dr es s e s ce oe we dat a vcc 55h 30 h t wc sa era s e c o m m a n d se qu en c e (l a s t t w o c y c l es ) va co mpl e t e ~ ~ ~ ~ va ~ ~ in pr ogr e s s ~ ~ ~ ~ ~ ~ ~ ~ t as t vc s r e ad s t a t us d a t a 2a ah t ah t wh wh 2 t ch t ghwl t wp t wph t cs t ds t dh not e : sa = sect or address. v a = va l i d add r e ss f o r r e ading s t a t u s dat a . 555 h f o r c h i p er ase 1 0h f o r chip er a s e preliminary (decemb e r, 20 04, versio n 0.2 ) 18 amic technology , corp.
a29040b series tim i ng wav e form s for data polling (during embedde d algorithm s) timing wav e forms for t oggle bit (during embedded algorith m s) note: va = valid ad dress; no t require d for i/o 6 . illustration sho w s first t w o status c y cle a fter command sequ ence, last status read c y cl e, and arra y d a ta rea d c y cl e. addresses ce oe we i/ o 7 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ c o mp l e m ent ~ ~ c o m p l e ment true v a lid d a ta hi gh-z st at us d a t a ~ ~ st at us d a t a true v a lid d a ta hi gh-z i/ o 0 - i / o 6 t ac c t ce t ch t oe t oeh t df t oh n o t e : va = va l i d address. i l l u st at i on show s f i rst st at us cyc l e af t e r com m an d seque nce, l a st st a t us read cycl e, and array dat a read cycl e. a ddre sse s ce oe we i/o 6 , i/o 2 t rc va va v a ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ v a l i d st at us t ac c t ce t ch t oe t oe h t df t oh va val i d s t at us v a lid s t a t u s v a lid s t a t u s ~ ~ (f i r st re ad) (sec ond rea d ) ( st op t o ggi ng) preliminary (decemb e r, 20 04, versio n 0.2 ) 19 amic technology , corp.
a29040b series tim i ng wav e form s for i/o 2 v s . i/ o 6 ac char ac te ristics eras e an d pro g r am op erati o n s alternate ce controlle d w r ites enter embedded erasing erase suspend enter erase suspend program erase resume we i/o 6 i/o 2 erase erase suspend read erase suspend read erase erase complete i/o 2 and i/o 6 toggle with oe and ce note : both i/o 6 and i/o 2 toggle with oe or ce. see the text on i/o 6 and i/o 2 in the section "write operation statue" for more information. ~ ~ ~ ~ ~ ~ erase suspend program ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ para mete r s y mbols speed j e d e c s t d de s c ription - 5 5 - 7 0 - 9 0 unit t av a v t wc w r ite c y cl e t i me (note 1) min. 55 70 90 ns t a vel t as a d d r e s s setu p t i m e min. 0 n s t el a x t ah a d d r e s s h o ld t i m e min. 4 0 4 5 4 5 n s t d veh t ds data setup t i me min. 25 30 45 ns t e hdx t dh data hol d t i me min. 0 ns t ghel t ghel read r e cov e r t i me before write min. 0 ns t wl el t ws we setup t i me min. 0 n s t eh wh t wh we hold t i me min. 0 n s t eleh t cp w r ite pulse w i dth min. 30 35 45 ns t eh el t cp h w r ite pulse w i dth hig h min. 20 20 20 ns t wh wh 1 t wh wh 1 b y te pro g ram m ing oper atio n (note 2) t y p. 7 s t wh wh 2 t wh wh 2 sector erase operatio n (not e 2) t y p. 1 sec notes: 1. not 100 % tested. 2. see the "eras e and progr am ming perfo rma nce" secti on fo r more informat i on. preliminary (decemb e r, 20 04, versio n 0.2 ) 20 amic technology , corp.
a29040b series tim i ng wav e form s for a l terna t e ce controlled write opera t ion erase and pr ogramming performa nce addresses we oe ce data 555 for program 2aa for erase pa d out ~ ~ ~ ~ i/o 7 ~ ~ ~ ~ ~ ~ data polling note : 1. pa = program address, pd = program data, sa = sector address, i/o 7 = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. pd for program 30 for sector erase 10 for chip erase ~ ~ t busy t whwh1 or 2 t ah t as t wc t wh t ghel t cp t ws t cph pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase t rh t ds t dh para mete r t y p . (no t e 1) max. (no t e 2) un it co mmen t s sector erase t i me 1 8 sec chip eras e t i me 8 64 sec excl ud es 00h programm i ng prior to eras ure (note 4) b y te pro g ram m ing t i me 35 300 s chip pro g ram m ing t i me (note 3) 3.6 10.8 sec excl ud es s y ste m-level overh ead (n ote 5) notes: 1. t y pic a l pr o g ram an d era s e times ass u me the fol l o w i ng c o n d itio n s : 25 c, 5.0v vcc, 100,0 0 0 c y c l es. add i tiona ll y, programm i ng t y p i cal l y assum e s checker boa rd pattern. 2. under w o rst case con d itio n s of 90 c, vcc = 4.5v (4.75v for -55), 100,0 00 c y c l es. 3. t he typic a l chip progr amm i ng tim e is co n s idera b l y less t han th e ma ximum chi p pro g r a mming tim e l i s ted, since mo st b y tes program f a ster than th e ma xi mum b y t e pr og ram time liste d . if the maxim u m b y t e pro g ra m time giv en is exc e e ded, onl y th e n does the d e vic e set i/o 5 = 1. see the sectio n on i/o 5 for further information. 4. in the pre-pr ogrammi ng ste p of the embed ded eras e alg o r ithm, all b y t e s are pro g ramm ed to 00h befor e erasur e. 5. s y stem- l eve l over hea d is t he time r e q u ire d to e x ecute th e four-b us-c ycl e comma nd s e que nce for pro g rammin g . see t able 4 for further infor m ation o n com m and d e finiti on s. 6. t he device has a gu arant e ed minim u m er ase an d progr a m c y cle e n d u ra nce of 100, 000 c y cles. preliminary (decemb e r, 20 04, versio n 0.2 ) 21 amic technology , corp.
a29040b series latc h-up ch arac teris t ics de s c r i p t i o n m i n . ma x . input voltage w i t h respect to vss on all i/o pins -1.0v vcc+ 1.0v vcc curre nt -100 ma + 100 ma includ es all p i n s exce pt vcc. t e st conditio n s : vcc = 5.0v, one p i n at time . tsop pin capacita nce para mete r s y mbol para mete r de scription te s t se tup ty p. max. unit c in i n p u t cap a cita n c e v in =0 6 7.5 pf c out output capac itance v out =0 8.5 12 pf c in2 control pi n ca pacita n ce v in =0 7.5 9 pf notes: 1. sample d, not 1 00% tested. 2. t e st conditio n s t a = 2 5 c, f = 1.0mhz plcc and p-dip pin capacitance para mete r s y mbol para mete r de scription te s t se tup ty p. m a x . u n i t c in input cap a cita nce v in =0 4 6 pf c out output capac itance v out =0 8 12 pf c in2 control pi n ca pacita n ce v pp =0 8 12 pf notes: 1. sample d, not 1 00% tested. 2. t e st conditio n s t a = 2 5 c, f = 1.0mhz da ta rete nti on para mete r te s t conditi o n s min unit 150 c 1 0 y e a r s minimum pattern data rete nti on t i me 125 c 2 0 y e a r s preliminary (decemb e r, 20 04, versio n 0.2 ) 22 amic technology , corp.
a29040b series test conditi ons t able 6. t e st specificati ons te s t conditi o n -5 5 a l l othe rs unit output loa d 1 t t l gate output loa d c apacit ance, c l (inclu din g jig c apacit ance) 30 100 pf input rise a nd f a ll t i mes 5 20 ns input pulse l e v els 0. 0 - 3.0 0.45 - 2.4 v input timing m easur ement ref e r enc e leve ls 1.5 0.8, 2.0 v output timing measurem ent r e fe renc e leve ls 1.5 0.8, 2.0 v 6.2 k ? device under test c l diodes = in3064 or equivalent 2.7 k ? 5.0 v figure 7. test setup preliminary (decemb e r, 20 04, versio n 0.2 ) 23 amic technology , corp.
a29040b series ordering information part no. a cces s tim e (ns) a c ti v e r ead current ty p. (m a ) progra m /erase current ty p. (m a ) sta ndby curre n t ty p. ( a ) pack ag e a290 40b-5 5 32pi n dip a290 40b-5 5f 32pi n pb-f ree dip a290 40bl- 55 32pi n plcc a290 40bl- 55f 32pi n pb-f ree plcc a290 40bv-5 5 32pi n t s op a290 40bv-5 5 f 32pi n pb-f ree t s op a290 40b-5 5u 32pi n dip a290 40b-5 5u f 32pi n pb-f ree dip a290 40bl- 55 u 32pi n plcc a290 40bl- 55 uf 32pi n pb-f ree plcc a290 40bv-5 5 u 32pi n t s op a290 40bv-5 5 u f 5 5 2 0 3 0 1 32pi n pb-f ree t s op a290 40b-7 0 32pi n dip a290 40b-7 0f 32pi n pb-f ree dip a290 40bl- 70 32pi n plcc a290 40bl- 70f 32pi n pb-f ree plcc a290 40bv-7 0 32pi n t s op a290 40bv-7 0 f 32pi n pb-f ree t s op a290 40b-7 0u 32pi n dip a290 40b-7 0u f 32pi n pb-f ree dip a290 40bl- 70 u 32pi n plcc a290 40bl- 70 uf 32pi n pb-f ree plcc a290 40bv-7 0 u 32pi n t s op a290 40bv-7 0 u f 7 0 2 0 3 0 1 32pi n pb-f ree t s op preliminary (decemb e r, 20 04, versio n 0.2 ) 24 amic technology , corp.
a29040b series ordering information (co n tinued ) part no. a cces s tim e (ns) a c ti v e r ead current ty p. (m a ) progra m /erase current ty p. (m a ) sta ndby curre n t ty p. ( a ) pack ag e a290 40b-9 0 32pi n dip a290 40b-9 0f 32pi n pb-f ree dip a290 40bl- 90 32pi n plcc a290 40bl- 90f 32pi n pb-f ree plcc a290 40bv-9 0 32pi n t s op a290 40bv-9 0 f 32pi n pb-f ree t s op a290 40b-9 0u 32pi n dip a290 40b-9 0u f 32pi n pb-f ree dip a290 40bl- 90 u 32pi n plcc a290 40bl- 90 uf 32pi n pb-f ree plcc a290 40bv-9 0 u 32pi n t s op a290 40bv-9 0 u f 9 0 2 0 3 0 1 32pi n pb-f ree t s op preliminary (decemb e r, 20 04, versio n 0.2 ) 25 amic technology , corp.
a29040b series packag e information p-dip 32l out line dimensio ns unit: inch es/mm 1 32 e a 2 a l e 1 e a d c b 1 b a 1 ba s e pl a n e s e a t i n g p l ane 16 17 e dimen s io ns in i n ches dimen s io ns in mm sy mbo l m i n n o m m a x m i n n o m m a x a - - 0.210 - - 5 . 3 3 4 a 1 0.015 - - 0.381 - - a 2 0 . 1 4 9 0.154 0.159 3.785 3.912 4 . 0 3 9 b - 0 . 0 1 8 - - 0 . 4 5 7 - b 1 - 0 . 0 5 0 - - 1 . 2 7 0 - c - 0 . 0 1 0 - - 0 . 2 5 4 - d 1 . 6 4 5 1.650 1.655 41.783 41.91 4 2 . 0 3 7 e 0 . 5 3 7 0.542 0.547 13.64 13.767 1 3 . 8 9 4 e 1 0 . 5 9 0 0.600 0.610 14.986 15.240 1 5 . 4 9 4 e a 0 . 6 3 0 0.650 0.670 16.002 16.510 1 7 . 0 1 8 e - 0 . 1 0 0 - - 2 . 5 4 0 - l 0 . 1 2 0 0.130 0.140 3.048 3.302 3 . 5 5 6 0 - 15 0 - 15 no tes: 1. t he maximum value of dimen s ion d inc l u des end flash. 2. dimens ion e d oes not inc l ud e resin fins. preliminary (decemb e r, 20 04, versio n 0.2 ) 26 amic technology , corp.
a29040b series packag e information plcc 3 2 l o u tline dim e n s ion unit: inch es/mm a 1 a 2 a e d y h d d 13 g d b 1 b g e c 5 14 20 21 29 30 32 1 4 e h e l dimen s io ns in i n ches dimen s io ns in mm sy mbol m i n n o m m a x m i n nom m a x a - - 0.134 - - 3 . 4 0 a 1 0 . 0 1 8 5 - - 0.47 - - a 2 0 . 1 0 5 0.110 0.115 2.67 2 . 8 0 2 . 9 3 b 1 0 . 0 2 6 0.028 0.032 0.66 0 . 7 1 0 . 8 1 b 0 . 0 1 6 0.018 0.021 0.41 0 . 4 6 0 . 5 4 c 0 . 0 0 8 0.010 0.014 0.20 0.254 0 . 3 5 d 0 . 5 4 7 0.550 0.553 13.89 13.97 1 4 . 0 5 e 0 . 4 4 7 0.450 0.453 11.35 11.43 1 1 . 5 1 e 0 . 0 4 4 0.050 0.056 1.12 1 . 2 7 1 . 4 2 g d 0 . 4 9 0 0.510 0.530 12.45 12.95 1 3 . 4 6 g e 0.390 0.410 0.430 9.91 10.41 10.92 h d 0.585 0.590 0.595 14.86 14.99 15.11 h e 0 . 4 8 5 0.490 0.495 12.32 12.45 1 2 . 5 7 l 0 . 0 7 5 0.090 0.095 1.91 2 . 2 9 2 . 4 1 y - - 0.003 - - 0 . 0 7 5 t 0 q - 10 q 0 q - 10 q no tes: 1. dimens ions d and e do not in clude r e sin fins . 2. dimens ions g d & g e are for pc board surfac e mount pa d pi tch desig n refere n c e onl y. preliminary (decemb e r, 20 04, versio n 0.2 ) 27 amic technology , corp.
a29040b series packag e information tsop 32l type i (8 x 20 mm) outline dimensions unit: inch es/mm e l e l a a 2 c d y d e t a il " a " s a 1 b h d d e d e t a il " a " dimen s io ns in i n ches dimen s io ns in mm sy mbol m i n n o m m a x m i n n o m m a x a - - 0.047 - - 1 . 2 0 a 1 0.002 - 0.006 0 . 0 5 - 0 . 1 5 a 2 0.037 0.039 0.041 0 . 9 5 1 . 0 0 1 . 0 5 b 0 . 0 0 7 0.009 0.011 0 . 1 8 0 . 2 2 0 . 2 7 c 0.004 - 0.008 0 . 1 1 - 0 . 2 0 d 0 . 7 2 0 0.724 0.728 18.30 18.40 1 8 . 5 0 e - 0.315 0.319 - 8 . 0 0 8 . 1 0 e 0.020 bsc 0.50 bsc h d 0 . 7 7 9 0.787 0.795 19.80 20.00 2 0 . 2 0 l 0 . 0 1 6 0.020 0.024 0 . 4 0 0 . 5 0 0 . 6 0 l e - 0.032 - - 0 . 8 0 - s - - 0.020 - - 0 . 5 0 y - - 0.003 - - 0 . 0 8 0 - 5 0 - 5 no tes: 1. t he maximum value of dimen s ion d i n cl udes end flash. 2. dimens ion e d oes not inc l ud e resin fins. 3. dimens ion s i n cludes end flas h. preliminary (decemb e r, 20 04, versio n 0.2 ) 28 amic technology , corp.

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